1. Field of the Invention
The present invention relates to a communication apparatus and an information transfer method for information transfer between memories in the communication apparatus.
2. Description of the Related Art
In a so-called TCP/IP (Transmission Control Protocol/Internet Protocol) protocol group, TCP is a connection type protocol. TCP connection is represented with a combination of 4 informations, respective IP addresses and TCP port numbers of two network devices. The combination of these informations is called a socket pair or simply called a socket.
In recent years, built-in devices to access a network with TCP/IP for improvement in users' convenience are rapidly increased. These devices have an HTTP server function to realize checking of the status of the built-in device, changing of settings, and transmission/reception of audio information, still and moving images, from an arbitrary PC on the network or mobile terminal (including a cellular phone).
On the other hand, the speed of communication media represented by Ethernet (registered trademark) is being dramatically increased. In accordance with the increase in the speed, there is a need for execution of network protocol processing at a high speed.
To attain the Full-wire speed in a gigabit Ethernet, a processor which operates at a frequency of about 3 GHz is required. However, the performance is far beyond that of processors generally installed in the current built-in devices. Then, generally, an auxiliary device specialized for protocol processing such as a TOE (TCP/IP offload engine) is added to the system, thereby broadband network communication is realized. U.S. Pat. No. 6,226,680 discloses a conventional TOE technique.
In the protocol processing, how to handle a PCB (Protocol Control Block), context information or a group of context information necessary for processing an arbitrary communication protocol. Particularly, in the TCP/IP protocol, the PCB is called a TCP Protocol Control Block, and is generally abbreviated to TCPPCB, TCPCB or TCB.
A TCPCB, constituted with several ten types of parameters (variables), is prepared for each connection. Further, upon reception of a TCP packet, it is necessary to make a search and determine a TCPCB to be used. Note that the respective elements of the TCPCB are variables frequently accessed during TCP processing.
In the invention disclosed in the U.S. Pat. No. 6,226,680, a PCB necessary for performing TCP processing is duplicated from a main memory onto a high-speed primary memory such as an SRAM (Static Random Access Memory) thereby access speed is increased. At this time, when the number of connections has been increased and all the PCBs are not held in the primary memory, replacement processing is performed between the main memory and the primary memory such that only necessary PCBs exist on the primary memory.
Further, Japanese Patent Application Laid-Open No. Sho 62-117050 discloses pipeline processing performed by plural processors on a protocol stack.
In the invention disclosed in the U.S. Pat. No. 6,226,680, it is necessary to make a search and determine a PCB to be used upon reception of TCP packet. The respective elements of the PCB are variables frequently accessed during TCP processing. For speeding up of the TCP processing, it is necessary to increase the speed of the search and access for/to the PCB.
Further, in the invention disclosed in Japanese Patent Application Laid-Open No. Sho 62-117050, a layered protocol stack such as TCP/IP is subjected to pipeline processing by plural processors. This is advantageous for increasing speed, however, it is necessary to configure the processing not to break down the pipeline processing.
It is expected to combine the both techniques and drastically speed up the protocol stack processing. However, in the conventional art, when a caching failure occurs upon access to a PCB, cache update is performed on demand, the pipeline processing is broken down. The caching failure frequently occurs when the cache size of the PCB is small in comparison with the number of connections. Further, in a built-in system, as the cache size of the PCB cannot be increased from the point of cost.
Further, in the HTTP server on the above-described built-in device, sequential arrival of communication packets in different connections is conceivable. Even in a system where PCBs are held in a high-speed accessible internal memory or cache memory for the purpose of speed-up of access to the PCBs, the PCBs are frequently replaced in the above situation. Accordingly, the advantage of caching of the PCB is lost, and the performance is seriously lowered.
Further, the frequent replacement of the PCBs bears upon the band of a data bus or the like in the built-in device, which reduces the performances of other services in the built-in device, and by extension, lowers the entire performance of the built-in device.
Further, in SSL/TLS communication, it is necessary to identify plural sessions and obtain PCBs for the sessions. The session corresponds to connection in TCP communication. Also, in the SSL/TLS communication, similar problems to those in the HTTP server occur.